This invention is in the field of integrated circuit manufacture. Embodiments of this invention are directed to metal-oxide-semiconductor (MOS) integrated circuits constructed with transistors of multiple threshold voltages.
An important parameter in defining the operation and performance of a MOS transistor is its threshold voltage (Vt). As fundamental in the art, the MOS transistor threshold voltage determines the gate-to-source voltage required to turn on the device (i.e., to conduct source/drain current) as well as the level of source/drain current for a given gate-to-source voltage when turned on. In a general sense, an enhancement mode MOS transistor with a low threshold voltage will switch faster but consume more power than will a similar transistor with a higher threshold voltage.
In modern electronic systems, particularly in portable and thus battery-powered systems such as wireless telephone handsets, power consumption is a significant concern. On the other hand, it is of course desirable to maximize system performance. Selection of the MOS transistor threshold voltage is thus a critical factor in achieving the desired performance level while not exceeding power constraints. The desired threshold voltage is implemented, in many cases, by ion implantation of a selected concentration of dopant into the eventual transistor channel regions. In complementary-MOS (“CMOS”) integrated circuits, this threshold voltage adjust implant may be performed for both n-channel and p-channel MOS transistors.
Many modern logic integrated circuits are constructed as multiple logic “blocks”, each block being an array or other arrangement of transistors available for interconnection at higher metal levels to realize a desired logic function. Some circuit blocks correspond to so-called “standard cells”, which are circuit blocks implementing commonly-used functions, ranging from logical primitives to entire processor cores. Considering the performance vs. power tradeoff discussed above, conventional block-based logic circuits are now commonly implemented with some blocks of low threshold voltage transistors and other blocks of higher threshold voltage devices. In this way, performance-critical circuits can be constructed using low-Vt devices that switch rapidly and conduct strongly, while non-critical-path devices can be constructed with higher threshold voltage devices to reduce the overall power consumption of the circuit.
In conventional manufacturing flows, at least the low Vt blocks, if not also the higher standard Vt blocks, receive the threshold adjust implant. For CMOS circuits, low Vt and high Vt blocks may be realized for both n-channel and p-channel transistors. Masked threshold adjust implants differentiate the low Vt and standard Vt blocks, with photoresist or another mask material protecting the regions of the integrated circuit that are not to receive a particular implant. From a layout perspective, additional space between devices of different threshold voltage for the implant mask pattern and the corresponding Vt adjust implant itself is conventionally provided to ensure that the Vt adjust implant reaches one block but not its neighbor.
FIGS. 1a and 1b illustrate, in plan view and in cross-sectional view, the spacing requirement in conventional integrated circuits between a logic block that is to receive a certain threshold adjust implant and a logic block that is to not receive that implant. In the integrated circuit of FIG. 1a, CMOS logic blocks are arranged in rows 10 and columns 11 in an array. Each row 10 of logic blocks includes both an n-type active region 4n and a p-type active region 4p. For example, a CMOS logic block in row 10(k) and column 11(j) of FIG. 1a includes n-type active region 4n′ and p-type active region 4p′. P-type active regions 4p are disposed within n-type well region 2, and n-type active regions 4n are disposed within p-type substrate 14 (FIG. 1b), in this single-well example. Alternatively, of course, a twin-well process could be used, in which case n-type active regions 4n would be disposed within a p-type well. In any case, the bounds of active regions 4n, 4p are determined by isolation structures 15 (FIG. 1b).
Polysilicon gate electrodes 6g overlie each of the active regions 4n, 4p, with those active regions 4n, 4p in the same CMOS logic block sharing a common gate electrode 6g. As known in the art, active regions 4n, 4p refer to regions of the surface of the substrate or well at which transistor source and drain regions can be formed, generally in a self-aligned manner relative to polysilicon gate electrode 6g. For example, active region 4p′ is p-type by virtue of a source/drain ion implantation and anneal performed after the formation of polysilicon gate electrodes 6g; the channel portion of the active region underlying gate electrode 6g will remain n-type in active region 4p, and p-type in active region 4n. 
Circuits can be formed within a given logic block by the placement of contacts CT and the routing of metal interconnects (not shown) to those contacts CT. FIG. 1a illustrates an example of the formation of a CMOS inverter in the logic block of row 10(k) and column 11(j). Contacts CT are formed through the overlying insulator layer to locations on either side of gate electrode 6g′ in active region 4p′, and also on either side of gate electrode 6g′ in active region 4n′. These contacts-to-active serve as connections to the source and drain of each of an n-channel and a p-channel transistor that share a common gate electrode 6g′. Another contact CT is made to gate electrode 6g′ itself, to serve as the input of the CMOS inverter; conversely, a metal conductor connection to the contacts CT at the drain of these transistors serves as the inverter output. Similarly, other CMOS circuits can be constructed by the placement of contacts CT and the routing of metal conductors to those contacts CT, as is well known in the art.
In the integrated circuit of FIGS. 1a and 1b, as in many modern integrated circuits having extremely small (e.g., sub-micron) minimum feature sizes, it is useful to photolithographically pattern and form certain elements with a great degree of regularity across the surface of the integrated circuit. This is evident in FIG. 1a by the routing of polysilicon gate electrodes 6g of constant width in the same direction, and at a relatively constant spacing, within each logic block. This regularity is commonly enforced by constraining the pitch (width plus spacing) of gate electrodes 6g relative to one another to within a relatively narrow range. For example, in modern deep submicron technologies in which gate electrode widths are on the order of 0.25 to 0.30 μm, the gate electrode pitch may be constrained to be within 114 nm to 128 nm.
This regularity, enforced by gate electrode pitch constraints, is also maintained between columns 11 of logic blocks by polysilicon elements 6c disposed between adjacent active regions 4p, 4n, and that overlie isolation structures 15 (FIG. 1b). These elements 6c have the same width and spacing as gate electrodes 6g, but are not electrically connected. By maintaining a generally constant feature pitch in this region of the integrated circuit, elements 6c assist in the patterning of gate electrodes 6g of uniform width and spacing, and thus the formation of transistors of matched electrical characteristics. Polysilicon elements 6c are of course formed simultaneously with gate electrodes 6g. 
In this conventional example, certain logic blocks are to be formed with a lower threshold voltage than those in adjacent logic blocks. This is shown in FIG. 1a by active regions 4p′, 4p″, 4n′, 4n″ in column 11(j), which are to be made available for low-Vt transistors. In this conventional case, the lower threshold voltage is to be defined by a Vt adjust ion implant (i.e., “pocket” implant) that is performed after the formation of gate electrodes 6g; FIG. 1a illustrates region 13 that receives this low-Vt adjust implant. Conversely, adjacent active regions 4n in columns 11(j−1), 11(j+1) on either side of active regions 4n′, 4n″ in column 11(j) will be formed as “standard Vt” regions, which will receive a different Vt adjust implant or is alternatively defined by a “blanket” implant prior to formation of gate electrodes 6g. Similarly, adjacent active regions 4p in columns 11(j−1), 11(j+1) on either side of active regions 4p′, 4p″ in column 11(j) will be formed as “standard Vt” regions; active regions 4p′, 4p″ in column 11(j) will receive a Vt adjust implant to reduce the threshold voltage of p-channel transistors in those regions.
As evident from FIG. 1a, an extended distance D is provided between the low-Vt n-type active regions 4p′, 4p″, 4n′, 4n″ and their adjacent n-type regions 4p, 4n in standard-Vt logic blocks. In this conventional approach, this extended distance D is necessary to allow the Vt adjust implant to reach the channel regions underlying gate electrodes 6g in active regions 4p′, 4p″, 4n′, 4n″, while still masking that implant from the standard Vt active regions 4p, 4n on either side of these low-Vt regions. In addition, this distance D is constrained to correspond to an integral number of pitch intervals of polysilicon elements 6c between gate electrodes 6g. In this conventional case, because the minimum spacing required for allowing the Vt adjust implant to reach the channel regions while still attaining good masking is greater than two polysilicon pitch intervals (e.g., of 114 nm to 128 nm each), the constraint of constant gate electrode pitch requires that two polysilicon structures 6c be placed between standard-Vt and low Vt logic blocks.
FIG. 1b illustrates the structure of FIG. 1a in cross-section, at a point in its manufacture at which the low-Vt adjust implant is being performed. In this example, photoresist mask 12 is disposed over active regions 4n in the standard Vt regions. Also in this example, as is conventional, the Vt adjust implants are performed at a relatively large angle φ from the vertical, either by way of an angled implant or a rotating disk implant; this large angle φ facilitates implant of dopant into the channel region underlying gate electrode 6g and gate dielectric 9. However, in order for photoresist mask 12 to be effective in blocking the implant into its channel regions (especially into the first device on the opposite side of active region 4n′), mask 12 must be of an adequate thickness H. Geometrically, as shown in FIG. 1b, the angle φ of the implant coupled with the thickness H of photoresist mask 12 determines the minimum distance required between adjacent logic blocks; as discussed above, the actual distance D is constrained by the constant pitch interval requirement, such that the distance between the closest gate electrodes 6g in adjacent logic blocks is an integral number of gate electrode pitch intervals. This distance D is, of course, wasted space from a circuit density standpoint, as the corresponding chip area cannot be used for any active circuitry. So long as the number and placement of the low-Vt logic blocks is known in advance, the number of instances of this extended distance D can be minimized. This is because adjacent logic blocks containing transistors of the same threshold voltage can be placed much more closely together, essentially limited only by the minimum isolation structure width required to isolate the neighboring active regions from one another.
Unfortunately, it has been observed in connection with this invention that, at the time of device layout in many block-oriented integrated circuits, the designer does not yet know which logic blocks will become the limiting path from the standpoint of performance, nor which logic blocks will dominate the overall power consumption of the integrated circuit. In other words, the designer may not be able to select which circuit functions are to be implemented in low-Vt blocks and which ought to be implemented in high-Vt blocks, at the time of layout. While it is possible to change the Vt adjust implant for a given block by changing the appropriate implant mask patterns, the spacing requirements between logic blocks having different threshold voltage transistors must be satisfied. Accordingly, in order to provide maximum flexibility in the assignment of threshold voltages to logic blocks, conventional integrated circuit layouts must implement the necessary spacing on the sides of all logic blocks that may potentially receive a different threshold adjust implant from that of its neighbor. Conversely, conserving chip area by limiting the number of potential low Vt blocks (thus providing fewer instances of the additional spacing) constrains design flexibility, and limits the optimization of performance and power. This additional space is of course wasted in those cases in which adjacent blocks receive the same threshold adjust implant.